A sample-and-hold (“S/H”) circuit (hereinafter referenced generically as a “S/H circuit”) has a signal input terminal, a S/H clock input terminal, and a held signal output terminal. The S/H circuit receives, on the signal input terminal, an electrical signal with one or more time varying attributes such as, for example, amplitude or phase, and receives a sampling clock on the S/H clock input terminal. In response to a sampling command event such as, for example, one of a rising or falling edge of the S/H clock, the S/H circuit takes and then holds, on the held signal output terminal, a sample of the input signal.
Sample and hold circuits are used in a wide variety of applications such as, for example, analog-to-digital converter (“ADC”) devices, by sampling a time-varying input signal and presenting the held value to the signal input terminal of the ADC, to meet the set-up and hold requirements of the ADC comparators. Another example application is a “de-glitcher” at the output of a digital-to-analog converter (“DAC”), to sample the DAC output at delay after the DAC clock that is sufficient to allow output glitches to settle.
The sample held on the held signal output terminal of the S/H circuit is, ideally, the exact value of the input signal that existed at an exact point in space, at an exact point in time, where “exact” means accurate to infinite precision.
It has been long known, however, to persons of ordinary skill in the arts pertaining to S/H circuits that actual operating S/H circuits suffer from various non-ideal characteristics by which the actual sample at a given time after the sampling instant is not, in fact, the exact value of the input signal that was extant at that instant. These non-ideal characteristics include, for example, sampling jitter, meaning the statistical variance of the time difference between the ideal hold clock event and the instant that the S/H actually holds the sampled value; acquisition time, meaning the time required for the S/H circuit to charge the hold capacitor to the sampled signal value: as well as charge injection; clock feedthrough and pedestal error.
Various known methods are directed to reducing or compensating, at least in part, one or more of the above-identified non-ideal characteristics of actual S/H circuits.
For example, the simplest signal switch component of an S/H circuit is a single transistor fabricated by a MOS process, such as a PMOS FET or NMOS FET. Each of the PMOS FET and NMOS FET is controlled by a clock signal that swings between the MOS supply voltage VDD and the system ground. One problem inherent in a single transistor PMOS FET or NMOS FET structure, though, is that FETs require a threshold gate-to-source voltage, generally termed VTH, to switch ON, meaning to form a conducting channel extending under the gate from the source to the drain. The lowest signal voltage that can be transferred by a PMOS device is therefore equal to 0+VTH, and the highest voltage for an NMOS device is therefore equal to VDD−VTH.
To avoid this inherent shortcoming, and to provide other benefits known in the arts pertaining to S/H circuits, the complementary MOSFET (CMOS) switch was introduced and is now well known in the S/H arts. A typical CMOS switch includes a PMOS FET and an NMOS FET, connected in parallel, with a clock connected to the PMOS FET gate and a complement of that clock connected to the NMOS FET gate. The parallel PMOS and NMOS FETs turn ON and OFF concurrently, subject to time differences between the edges of the CLK and NCLK.
Related art CMOS S/H switch circuits, however, have inherent shortcomings. One is a signal-dependent ON resistance, which causes the related art. CMOS S/H switch circuits have an inherent non-linearity.
Various methods directed at this inherent non-linearity of CMOS switches have been long known. All have also been long known as having significant shortcomings. For example, one method is to significantly boost the gate control voltage “VG,” which lowers the “(VG−VS)/VS” variation caused by the signal variation at the source “VS” of the MOS switch. Boosting the gate voltage, though, has limited effectiveness. Further, the increased gate voltage often results in an increased risk of accelerated device failure.
Another of these methods, often referenced as the “bootstrap” method, makes the gate voltage follow the analog input signal with an offset to turn the switch ON and to keep “VGS” constant, thereby maintaining a somewhat constant ON resistance. However, the offset voltage must be high enough to turn the switch ON with low on-resistance but, at the same time, must be low enough to limit the stress added on the gate to be lower than the breakdown level.
Another limitation of the bootstrap method, long known in the arts pertaining to S/H circuits, is that the bootstrap circuitry controls “VGS”, but provides nothing to control the source-to-body voltage dependence, or VSB dependence of the MOS devices on-resistance in the CMOS switch. VSB dependence of the on-resistance is another linearity error source. Conventional methods directed to reducing “VSB” related linearity error include forcing the error to zero by shorting the body terminals of MOS FETs to their source terminals while in the sample mode. This method, though, has been long known as not attaining S/H circuit performance that is acceptable for many applications.